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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mpc17511a rev 2.0, 4/2007 freescale semiconductor technical data ? freescale semiconductor, in c., 2007. all rights reserved. 1.0 a 6.8 v h-bridge motor driver ic the 17511a is a monolithic h-bridge designed to be used in portable electronic applications to control small dc motors or bipolar step motors. end applications incl ude head positioners (cdrom or disk drive), camera focus moto rs, and camera shutter solenoids. the 17511a can operate efficiently with supply voltages as low as 2.0 v to as high as 6.8 v. its low r ds(on) h-bridge output mosfets (0.46 ? typical) can provide continuos motor drive currents of 1.0 a and handle peak currents up to 3.0 a. it is easily interfaced to low- cost mcus via parallel 3.0 v- or 5. 0 v- compatible logic. the device can be pulse width modulated (pwm-ed) at up to 200 khz. this device contains an integrated charge pump and level shifter (for gate drive voltages), integr ated shoot-through cu rrent protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. the 17511a has four operating mo des: forward, reverse, brake, and tri-stated (high impedance). features ? 2.0 v to 6.8 v continuous operation ? output current 1.0 a (dc), 3.0 a (peak) ? mosfets < 600 m ? r ds(on) @ 25 c guaranteed ? 3.0 v/ 5.0 v ttl- / cmos-compatible inputs ? pwm frequencies up to 200 khz ? undervoltage shutdown ? cross-conduction suppression ? low power consumption ? pb-free packaging designated by suffix codes ev and ep figure 1. 17511a simplified application diagram h-bridge motor driver ic ev suffix (pb-free) 98ash70109a 16-pin vmfp 17511a ordering information device temperature range (t a ) package mpc17511aev/el -20c to 65c 16 vmfp mpc17511aep/ r2 24 qfn ep suffix (pb-free) 98arl10577d 24-pin qfn vdd cres c1l c1h c2l c2h in2 in1 en out2 out1 gout vm gnd mcu gin motor 5.0 v 15 v 17511a
analog integrated circuit device data 2 freescale semiconductor 17511a internal block diagram internal block diagram figure 2. 17511a simplified internal block diagram c2h v dd c1l gout vm out1 out2 pgnd lgnd c2l c1h cres v dd in1 in2 en level control v dd logic shifter predriver charge pump low- voltage shutdown gin
analog integrated circuit device data freescale semiconductor 3 17511a pin connections pin connections figure 3. vmfp pin connections table 1. vmfp pin function description pin number pin name formal name definition 1 c2l charge pump 2l charge pump bucket capacitor 2 (negative pole). 2 c1h charge pump 1h charge pump bucket capacitor 1 (positive pole). 3 c1l charge pump 1l charge pump bucket capacitor 1 (negative pole). 4 vm motor drive power supply driver power supply voltage input pin. 5 vdd logic supply control circuit power supply pin. 6 in1 input control 1 control signal input 1 7 in2 input control 2 control signal input 2. 8 en enable control enable control signal input pin. 9 lgnd logic ground logic ground pin. 10 gin gate driver input low = true control signal for gout pin. 11 out1 h-bridge output 1 driver output 1 (right half of h-bridge). 12 pgnd power ground driver ground pin. 13 out2 h-bridge output 2 driver output 2 (left half of h-bridge). 14 gout gate driver output output gate driver signal to external mosfet switch. 15 cres charge pump output capacitor connection charge pump reservoir capacitor pin. 16 c2h charge pump 2h charge pump bucket capacitor 2 (positive pole). 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 cres gout out2 pgnd out1 gin lgnd c2l c1h c1l vm v dd in1 in2 en c2h
analog integrated circuit device data 4 freescale semiconductor 17511a pin connections figure 4. qfn pin connections table 2. qfn pin function description pin number pin name formal name definition 1, 2, 3, 4 vm motor drive power supply driver power supply voltage input pin. 5, 6, 13, 18 nc no connect this pin is not used. 7 vdd logic supply control circuit power supply pin. 8 in1 logic input control 1 control signal input 1. 9 in2 logic input control 2 control signal input 2. 10 en enable control enable control signal input pin. 11 lgnd logic ground logic ground pin. 12 gin gate driver input low = true control signal for gout pin. 14 out1 output 1 driver output 1 (right half of h-bridge). 15, 16 pgnd power ground driver ground pin. 17 out2 output 2 driver output 2 (left half of h-bridge). 19 gout gate driver output output gate driver signal to external mosfet switch. 20 cres pre-driver power supply pre-driver circuit power supply pin. 21 c2h charge pump 2h charge pump bucket capacitor 2 (positive pole). 22 c2l charge pump 2l charge pump bucket capacitor 2 (negative pole). 23 c1h charge pump 1h charge pump bucket capacitor 1 (positive pole). 24 c1l charge pump 1l charge pump bucket capacitor 1 (negative pole). 1 2 3 4 5 6 vm vm vm nc nc vm 7 8 9 10 11 12 v dd in2 en lgnd gin in1 18 17 16 15 14 13 nc pgnd pgnd out1 nc out2 19 20 21 22 23 24 gout c2h c2l c1h c1l cres
analog integrated circuit device data freescale semiconductor 5 17511a electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unle ss otherwise noted. exceedi ng the ratings may cause a malfunction or permanent damage to the device. rating symbol value unit motor supply voltage v m -0.5 to 8.0 v charge pump output voltage v cres -0.5 to 14.0 v logic supply voltage v dd -0.5 to 7.0 v signal input voltage (en, in1, in2, gin ) v in -0.5 to v dd + 0.5 v driver output current continuous peak (1) i o i opk 1.0 3.0 a esd voltage (2) human body model machine model v esd1 v esd2 1800 100 v storage temperature range t stg -65 to 150 c operating ambient temperature t a -20 to 65 c operating junction temperature t j -20 to 150 c thermal resistance (3) r ja 150 c/w power dissipation (4) p d 830 mw soldering temperature (5) t solder 260 c peak package reflow temperature during reflow (6) , (7) t pprt note 7 c notes 1. t a = 25 c, 10 ms pulse width at 200 ms intervals. 2. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 3. 37 x 50 x 1.6 [mm] glass epoxy board mount. 4. maximum at t a = 25 c. 5. soldering temperature limit is for 10 se conds maximum duration. not designed for i mmersion soldering. exceeding these limits may cause malfunction or permanent damage to the device. 6. pin soldering temperature limit is for 10 seconds maximum duration. not designed fo r immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 7. freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 17511a electrical characteristics static electrical characteristics static electrical characteristics table 4. static electrical characteristics characteristics noted under conditions t a = 25 c, v m = v dd = 5.0 v, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power driver circuit power supply voltage v m 2.0 5.0 6.8 v logic supply voltage v dd 2.7 5.0 5.7 v capacitor for charge pump c1, c2, c3 0.01 0.1 1.0 f standby power supply current motor supply standby current logic supply standby current (8) i v mstby i v ddstby ? ? ? ? 1.0 1.0 a ma operating power supply current logic supply current (9) charge pump circuit supply current i v dd i c res ? ? ? ? 3.0 0.7 ma ma low v dd detection voltage (10) v dd det 1.5 2.0 2.5 v driver output on resistance (11) r ds(on) ? 0.46 0.60 ? gate drive gate drive voltage (12) no current load v c res 12 13 13.5 v gate drive ability (internally supplied) i c res = -1.0 ma v c resload 10 11.2 ? v gate drive output i out = -50 a l in = 50 a v gouthigh v goutlow v c res - 0.5 lgnd v c res - 0.1 lgnd + 0.1 v c res lgnd + 0.5 v control logic logic input voltage v in 0?v dd v logic input function (2.7 v < v dd < 5.7 v) high-level input voltage low-level input voltage high-level input current low-level input current v ih v il i ih i il v dd x 0.7 ? ? -1.0 ? ? ? ? ? v dd x 0.3 1.0 ? v v a a pull-up resistance (en, gin ) r pu 50 100 200 k ? notes 8. i v ddstby includes current to the predriver circuit. 9. i v dd includes current to the predriver circuit. 10. detection voltage is defined as when the output becomes high-impedance after v dd drops below the detection threshold. when the gate voltage v c res is applied from an external source, v c res = 7.5 v. 11. i o = 1.0 a source + sink. 12. input logic signal not present.
analog integrated circuit device data freescale semiconductor 7 17511a electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electrical characteristics characteristics noted under conditions t a = 25 c, v m = v dd = 5.0 v, gnd = 0 v unless otherw ise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit input (en, in1, in2, gin ) pulse input frequency f in ? ? 200 khz input pulse rise time (13) t r ? ? 1.0 (14) s input pulse fall time (15) t f ? ? 1.0 (14) s output propagation delay time turn-on time turn-off time t plh t phl ? ? 0.55 0.55 1.0 1.0 s gout propagation delay time turn-on time turn-off time t son t soff ? ? 0.15 0.15 0.5 0.5 s charge pump circuit (16) rise time (17) t vcreson ?0.13.0 ms low-voltage detection time t vdddet ??10ms notes 13. time is defined between 10% and 90%. 14. that is, the input waveform slope must be steeper than this. 15. time is defined between 90% and 10%. 16. when c1 = c2 = c3 = 0.1 f. 17. time to charge c res to 11 v after application of v dd .
analog integrated circuit device data 8 freescale semiconductor 17511a electrical characteristics timing diagrams timing diagrams figure 5. t plh , t phl , and t pzh timing figure 6. low-voltage detection t plh 10% en, in1, in2 out1, out2 50% 90% (gin ) (gout) (t son ) t phl (t soff ) t v dd det 0% i m 50% 90% v dd deton v dd detoff t v dd det (<1.0 a) v dd 0.8 v/ 1.5 v 2.5 v/3.5 v table 6. truth table input output en in1 in2 gin out1 out2 gout hhhx l l x hhl xh l x hlhxlh x hllxzz x lxxxl l l hxxhxx l hxxlxx h h = high. l = low. z = high impedance. x = don?t care.
analog integrated circuit device data freescale semiconductor 9 17511a functional description introduction functional description introduction the 17511a is a monolithic h-bridge power ic applicable to small dc motors used in portable electronics. the 17511a can operate efficiently with supply voltages as low as 2.0 v to as high as 6.8 v, and it can provide continuos motor drive currents of 1.0 a while handling p eak currents up to 3.0 a. it is easily interfaced to low-cost mcus via parallel 3.0 v- or 5.0 v-compatible logic. the device can be pulse width modulated (pwm-ed) at up to 200 khz. the 17511a has four operating modes: forward, reve rse, brake, and tri-state (high impedance). basic protection and operati onal features (direction, dynamic braking, pwm control of speed and torque, main power supply undervoltage detection and shutdown, logic power supply undervoltage detection and shutdown), in addition to the 1.0 a rms outpu t current capability, make the 17511a a very attractive, co st-effective solution for controlling a broad range of small dc motors. in addition, a pair of 17511a devices can be used to control bipolar step motors. the 17511a can also be used to excite transformer primary windings with a switched square wave to produce secondary winding ac currents. as shown in figure 2, 17511a simplified internal block diagram , page 2 , the 17511a is a monolithic h-bridge with built-in charge pump circuitry. for a dc motor to run, the input conditions need to be set as follows: enable input logic high, one input logic low, and the other input logic high (to define output polarity). th e 17511a can execute dynamic braking by setting both in1 and in2 logic high, causing both low-side mosfets in the output h-bridge to turn on. dynamic braking can also implemented by taking the enable logic low. the output of the h-bridge can be set to an open- circuit high-impedance (z) condition by taking both in1 and in2 logic low. (refer to table 6, truth table , page 8 ). the 17511a outputs are capable of providing a continuous dc load current of up to 1.2 a. an internal charge pump supports pwm frequencies to 200 khz. the en pin also controls the charge pump, turni ng it off when en = low, thus allowing the 17511a to be placed in a power-conserving sleep mode. functional pin description out1 and out2 the out1 and out2 pins provide the connection to the internal power mosfet h-bridge of the ic. a typical load connected between these pins would be a small dc motor. these outputs will connect to ei ther vm or pgnd, depending on the states of the control inputs (refer to table 6, truth table , page 8 ). pgnd and lgnd the power and logic ground pins (pgnd and lgnd) should be connected together with a very low-impedance connection. cres the cres pin provides the connection for the external reservoir capacitor (output of th e charge pump). alternatively this pin can also be used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. the voltage at the cres pin will be approximately three times the v dd voltage, as the internal charge pump utilizes a voltage tripler circuit. the vcres voltage is used by the ic to supply gate drive for the internal power mosfet h-bridge. vm the vm pins carry the main su pply voltage and current into the power sections of the ic. this supply then becomes controlled and/or modulated by th e ic as it delivers the power to the load attached between out1 and out2. all vm pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. vm has an undervoltage threshold. if the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins. in1, in2, and en the in1, in2, and en pins are input control pins used to control the outputs. these pins are 5.0 v cmos-compatible inputs with hysteresis. the in1, in2, and en work together to control out1 and out2 (refer to table 6, truth table ). gin the gin input controls the gout pin. when gin is set logic low, gout supplies a level-shifted high-side gate drive signal to an external mosfet. when gin is set logic high, gout is set to gnd potential. c1l and c1h, c2l and c2h these two pairs of pins, the c1l and c1h and the c2l and c2h, connect to the external bucket capacitors required by the internal charge pump. the typical value for the bucket capacitors is 0.1 f.
analog integrated circuit device data 10 freescale semiconductor 17511a functional description functional pin description gout the gout output pin provides a level-shifted, high-side gate drive signal to an external mosfet with c iss up to 500 pf. vdd the vdd pin carries the 5.0 v supply voltage and current into the logic sections of the ic. vdd has an undervoltage threshold. if the supply volt age drops below the undervoltage threshold, the output power st age switches to a tri-state condition. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins.
analog integrated circuit device data freescale semiconductor 11 17511a typical applications functional pin description typical applications figure 7 shows a typical application for the 17511a. when applying the gate voltage to the cres pin from an external source, be sure to connect it vi a a resistor equal to, or greater than, r g = v c res / 0.02 ? . figure 7. 17511a typical application diagram cemf snubbing techniques care must be taken to protect the ic from potentially damaging cemf spikes induced when commutating currents in inductive loads. typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply pin (vm) (see figure 8 ). figure 8. cemf snubbing techniques mcu 17511a 5.0 v gnd c1l c1h c2l c2h cres en gin in1 in2 vm v dd out1 out2 motor gout solenoid r g > v c res /0.02 ? v c res < 14 v r g nc nc nc nc 0.01 f nc = no connect 17511a 5.0 v 5.0 v c1l c1h c2l c2h c res vm v dd out1 out2 17511a 5.0 v 5.0 v c1l c1h c2l c2h c res vm v dd out1 out2 gnd gnd
analog integrated circuit device data 12 freescale semiconductor 17511a packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ev (pb-free) suffix 16-pin vmfp plastic package 98ash70109a issue a
analog integrated circuit device data freescale semiconductor 13 17511a packaging package dimensions package dimensions (continued) ep (pb-free) suffix 24-lead qfn non-leaded package 98arl10577d issue a
analog integrated circuit device data 14 freescale semiconductor 17511a packaging package dimensions package dimensions (continued)
analog integrated circuit device data freescale semiconductor 15 17511a revision history revision history revision date description of changes 2.0 4/2007 ? implemented revision history page ? converted to freescale format ? added peak package reflow temperature during re flow (solder reflow) parameter and note with instructions from www.freescale.com to maximum ratings table 3
mpc17511a rev 2.0 4/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp .

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